Add support for Cortex-A57 erratum 829520 workaround

Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439

diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md
index 5d34409fd1b834636e794e17bd85a2a79134ba8d..94d05d574d071f4a474f9531efd463139412aa2f 100644 (file)
--- a/docs/cpu-specific-build-macros.md
+++ b/docs/cpu-specific-build-macros.md
@@ -66,6 +66,9 @@ For Cortex-A57, following errata build flags are defined :
 *   `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57
      CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
 
+*   `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57
+     CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
+
 3.  CPU Specific optimizations
 ------------------------------
 

diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index 68d0821cfb4f2956a60b20938a47f660ce41b893..95c1f56c1726ea0bdd23e211932af84fbea30fb6 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -67,6 +67,7 @@
 #define CPUACTLR_DCC_AS_DCCI           (1 << 44)
 #define CPUACTLR_DIS_STREAMING         (3 << 27)
 #define CPUACTLR_DIS_L1_STREAMING      (3 << 25)
+#define CPUACTLR_DIS_INDIRECT_PREDICTOR        (1 << 4)
 
 /*******************************************************************************
  * L2 Control register specific definitions.

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index ec32ce78df697da4400c58f7cd31c8e210ab74ce..25def1cddaca485605c7ef19d547a0c38c011046 100644 (file)
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -225,6 +225,32 @@ apply_828024:
        ret
 endfunc errata_a57_828024_wa
 
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A57 Errata #829520.
+        * This applies only to revision <= r1p2 of Cortex A57.
+        * Inputs:
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Clobbers : x0 - x5
+        * ---------------------------------------------------
+        */
+func errata_a57_829520_wa
+       /*
+        * Compare x0 against revision r1p2
+        */
+       cmp     x0, #0x12
+       b.ls    apply_829520
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+       b       print_revision_warning
+#else
+       ret
+#endif
+apply_829520:
+       mrs     x1, CPUACTLR_EL1
+       orr     x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR
+       msr     CPUACTLR_EL1, x1
+       ret
+endfunc errata_a57_829520_wa
+
        /* -------------------------------------------------
         * The CPU Ops reset function for Cortex-A57.
         * Clobbers: x0-x5, x15, x19, x30
@@ -267,6 +293,12 @@ func cortex_a57_reset_func
        mov     x0, x15
        bl      errata_a57_828024_wa
 #endif
+
+#if ERRATA_A57_829520
+       mov     x0, x15
+       bl      errata_a57_829520_wa
+#endif
+
        /* ---------------------------------------------
         * Enable the SMP bit.
         * ---------------------------------------------

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 7d9f2b72dc088aba22c545830f276077242a1acb..62de70f5144e9a951b4e6480c34b7a25f32c7e4b 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -82,6 +82,10 @@ ERRATA_A57_826974    ?=0
 # only to revision <= r1p1 of the Cortex A57 cpu.
 ERRATA_A57_828024      ?=0
 
+# Flag to apply erratum 829520 workaround during reset. This erratum applies
+# only to revision <= r1p2 of the Cortex A57 cpu.
+ERRATA_A57_829520      ?=0
+
 # Process ERRATA_A53_826319 flag
 $(eval $(call assert_boolean,ERRATA_A53_826319))
 $(eval $(call add_define,ERRATA_A53_826319))
@@ -105,3 +109,7 @@ $(eval $(call add_define,ERRATA_A57_826974))
 # Process ERRATA_A57_828024 flag
 $(eval $(call assert_boolean,ERRATA_A57_828024))
 $(eval $(call add_define,ERRATA_A57_828024))
+
+# Process ERRATA_A57_829520 flag
+$(eval $(call assert_boolean,ERRATA_A57_829520))
+$(eval $(call add_define,ERRATA_A57_829520))